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DSD
2006
IEEE
126views Hardware» more  DSD 2006»
16 years 13 days ago
Off-Line Testing of Delay Faults in NoC Interconnects
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimu...
DATE
1999
IEEE
105views Hardware» more  DATE 1999»
15 years 10 months ago
Identification and Exploitation of Symmetries in DSP Algorithms
In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit thes...
C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman...
LCN
1999
IEEE
15 years 10 months ago
An Integrated Software Immune System: A Framework for Automated Network Management, System Health, and Security
Maintaining the integrity of large-scale networks is becoming an increasingly daunting task as networks expand at an unprecedented rate. The majority of present network monitoring...
Michael Gilfix
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
16 years 3 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
ICCV
2009
IEEE
16 years 11 months ago
Super-Resolution from a Single Image
Methods for super-resolution can be broadly classified into two families of methods: (i) The classical multi-image super-resolution (combining images obtained at subpixel misali...
Daniel Glasner, Shai Bagon, Michal Irani