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VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
16 years 7 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
16 years 7 months ago
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...
Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo
VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
16 years 7 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
CVPR
2010
IEEE
2248views Computer Vision» more  CVPR 2010»
16 years 3 months ago
Morphological Snakes
We introduce a morphological approach to curve evolution. The differential operators used in the standard PDE snake models can be approached using morphological operations...
Luis Álvarez, Luis Baumela, Pedro Henríquez, Pab...
ICDM
2009
IEEE
172views Data Mining» more  ICDM 2009»
16 years 1 months ago
Sparse Least-Squares Methods in the Parallel Machine Learning (PML) Framework
—We describe parallel methods for solving large-scale, high-dimensional, sparse least-squares problems that arise in machine learning applications such as document classificatio...
Ramesh Natarajan, Vikas Sindhwani, Shirish Tatikon...