Sciweavers

1279 search results - page 183 / 256
» Fast Implementations of Automata Computations
Sort
View
IEEEPACT
2006
IEEE
16 years 6 days ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
15 years 11 months ago
Progressive scrambling for MP3 audio
– Audio scrambling can be employed in audio distribution for the purpose of guaranteeing the confidentiality. Electronic commerce in audio products would be facilitated by the de...
Wei-Gang Fu, Wei-Qi Yan, Mohan S. Kankanhalli
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 11 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
DASIP
2010
15 years 1 months ago
RVC: A multi-decoder CAL Composer tool
The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of component...
Francesca Palumbo, Danilo Pani, Emanuele Manca, Lu...
ANCS
2007
ACM
15 years 10 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy