308 search results - page 46 / 62 » Fast Comparisons of Circuit Implementations |
153
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CIIA
2009
15 years 7 months ago
2009
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
138
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FPGA
2005
ACM
15 years 11 months ago
2005
ACM
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
196
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DAC
2008
ACM
15 years 7 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
200
Voted
ACL2
2006
ACM
15 years 12 months ago
2006
ACM
We have developed an extension of ACL2 that includes the implementation of hash-based association lists and function memoization; this makes some algorithms execute more quickly. ...
166
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ICDM
2005
IEEE
15 years 11 months ago
2005
IEEE
Binary classification is a core data mining task. For large datasets or real-time applications, desirable classifiers are accurate, fast, and need no parameter tuning. We presen...