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VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
16 years 7 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
16 years 28 days ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
16 years 27 days ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
IPPS
2005
IEEE
16 years 4 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
DATE
1998
IEEE
103views Hardware» more  DATE 1998»
15 years 10 months ago
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets
Petri nets are a graph-based formalism appropriate to model concurrentsystems such as asynchronouscircuits or network protocols. Symbolic techniques based on Binary Decision Diagr...
Enric Pastor, Jordi Cortadella