1862 search results - page 90 / 373 » FPGA |
164
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
180
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ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
157
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
155
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—IP-XACT is a standard for describing intellectual property metadata for System-on-Chip (SoC) integration. Reesearchers have proposed visualizing and abstracting IP-XACT objects ...
185
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RECONFIG
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...