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ISCAS
1993
IEEE
133views Hardware» more  ISCAS 1993»
15 years 10 months ago
An efficient FIR filter architecture
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
Joseph B. Evans
ARC
2007
Springer
140views Hardware» more  ARC 2007»
15 years 10 months ago
Reconfigurable Computing for Accelerating Protein Folding Simulations
Abstract. This paper presents a methodology for the design of a reconfigurable computing system applied to a complex problem in molecular Biology: the protein folding problem. An e...
Nilton B. Armstrong, Heitor S. Lopes, Carlos R. Er...
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
15 years 10 months ago
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
Abstract - This paper presents a fast and accurate global routing algorithm, DpRouter, based on two efficient techniques: (1) dynamic pattern routing (Dpr), and (2) segment movemen...
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, ...
FPL
2009
Springer
100views Hardware» more  FPL 2009»
15 years 10 months ago
A virus scanning engine using a parallel finite-input memory machine and MPUs
This paper presents a virus scanning engine. After showing the difference between ClamAV (an anti-virus software) and SNORT (an intrusion detection software), we show a new archit...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...
ICCTA
2007
IEEE
15 years 10 months ago
Faster Placer for Island-Style FPGAs
In this paper, we propose a placement method for islandstyle FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature Simulated Anne...
Pritha Banerjee, Susmita Sur-Kolay