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FPL
2006
Springer
94views Hardware» more  FPL 2006»
15 years 10 months ago
Sizing of Processing Arrays for FPGA-Based Computation
Computing applications in FPGAs are commonly built from repetitive structures of computing and/or memory elements. In many cases, application performance depends on the degree of ...
Tom Van Court, Martin C. Herbordt
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
15 years 10 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
FPGA
2000
ACM
168views FPGA» more  FPGA 2000»
15 years 10 months ago
A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions
This paper presents a benchmark suite for evaluating a configurable computing system's infrastructure, both tools and architecture. A novel aspect of this work is the use of ...
S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Na...
FPGA
2000
ACM
114views FPGA» more  FPGA 2000»
15 years 10 months ago
Generating highly-routable sparse crossbars for PLDs
A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to ac...
Guy G. Lemieux, Paul Leventis, David M. Lewis
FPGA
2000
ACM
119views FPGA» more  FPGA 2000»
15 years 10 months ago
Timing-driven placement for FPGAs
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
Alexander Marquardt, Vaughn Betz, Jonathan Rose