1862 search results - page 109 / 373 » FPGA |
185
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
190
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ITC
2002
IEEE
15 years 11 months ago
2002
IEEE
: We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either...
163
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
129
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FCCM
2000
IEEE
15 years 10 months ago
2000
IEEE
For multiple FPGA systems, the limited number of I/O pins causes many problems. To solve these problems, efficient communication scheduling among FPGAs is crucial for obtaining hi...
167
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DFT
1999
IEEE
15 years 10 months ago
1999
IEEE
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...