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GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
15 years 11 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
118
Voted
MSE
2003
IEEE
97views Hardware» more  MSE 2003»
15 years 11 months ago
Harnessing FPGAs for Computer Architecture Education
Computer architecture is often taught by having students use software to design and simulate individual pieces of a computer processor. We have developed a method that will take t...
Mark Holland, James Harris, Scott Hauck
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
16 years 2 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
FPGA
1998
ACM
142views FPGA» more  FPGA 1998»
15 years 10 months ago
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
IPPS
2006
IEEE
15 years 12 months ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...