Sciweavers

4155 search results - page 569 / 831
» External Memory Algorithms
Sort
View
ICNP
2006
IEEE
16 years 19 days ago
High Speed Pattern Matching for Network IDS/IPS
— The phenomenal growth of the Internet in the last decade and society’s increasing dependence on it has brought along, a flood of security attacks on the networking and compu...
Mansoor Alicherry, Muthusrinivasan Muthuprasanna, ...
INFOVIS
2005
IEEE
16 years 6 days ago
PRISAD: A Partitioned Rendering Infrastructure for Scalable Accordion Drawing
We present PRISAD, the first generic rendering infrastructure for information visualization applications that use the accordion drawing technique: rubber-sheet navigation with gu...
James Slack, Kristian Hildebrand, Tamara Munzner
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
16 years 4 days ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
GECCO
2004
Springer
155views Optimization» more  GECCO 2004»
15 years 12 months ago
Genetic Network Programming with Reinforcement Learning and Its Performance Evaluation
A new graph-based evolutionary algorithm named “Genetic Network Programming, GNP” has been proposed. GNP represents its solutions as directed graph structures, which can improv...
Shingo Mabu, Kotaro Hirasawa, Jinglu Hu
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
15 years 12 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...