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FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
16 years 10 days ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
ISCAS
2003
IEEE
83views Hardware» more  ISCAS 2003»
16 years 2 days ago
An Integrated Framework of Design Optimization and Space Minimization for DSP applications
This paper presents an Integrated Framework of Design Optimization and Space Minimization (IDOM) for generating the minimum number of functional units with schedule length and mem...
Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Cha...
IPPS
1999
IEEE
15 years 11 months ago
Linear Aggressive Prefetching: A Way to Increase the Performance of Cooperative Caches
Cooperative caches offer huge amounts of caching memory that is not always used as well as it could be. We might find blocks in the cache that have not been requested for many hou...
Toni Cortes, Jesús Labarta
VISUALIZATION
1996
IEEE
15 years 11 months ago
Isosurfacing in Span Space with Utmost Efficiency (ISSUE)
We present efficient sequential and parallel algorithms for isosurface extraction. Based on the Span Space data representation, new data subdivision and searching methods are desc...
Han-Wei Shen, Charles D. Hansen, Yarden Livnat, Ch...
ICRA
1993
IEEE
101views Robotics» more  ICRA 1993»
15 years 11 months ago
Measuring Complexity of Intelligent Machines
In this paper we introduce a formalism which combines reliability and complexity as performance measures for Intelligent Machines. For a given desired reliability, di erent algori...
Pedro U. Lima, George N. Saridis