4155 search results - page 417 / 831 » External Memory Algorithms |
189
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SAC
2006
ACM
16 years 24 days ago
2006
ACM
In this paper, we describe the design and implementation of a tuple-based distributed memory realized with the use of RFID technology. The key idea – rooted in a more general sc...
177
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GLVLSI
2005
IEEE
16 years 14 days ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
161
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SC
2004
ACM
16 years 8 days ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
193
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CSMR
1999
IEEE
15 years 11 months ago
1999
IEEE
Maintenance activities are made more difficult when pointers are heavily used in source code: the programmer needs to build a mental model of memory locations and of the way they ...
227
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CASES
2007
ACM
15 years 11 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...