4155 search results - page 415 / 831 » External Memory Algorithms |
197
click to vote
ISPDC
2010
IEEE
15 years 5 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
141
click to vote
ICIP
2009
IEEE
16 years 8 months ago
2009
IEEE
In implementing an efficient block coder for JPEG2000, the memories required for storing the state variables dominate the hardware cost of a block coder. In this paper, we propose...
196
click to vote
DAC
2007
ACM
16 years 7 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
162
click to vote
DAC
2000
ACM
16 years 7 months ago
2000
ACM
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
170
click to vote
DAC
2006
ACM
16 years 7 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...