In this paper, we introduce RICE, a graphical application for interacting with the description logic inference server Racer. Comparing RICE with OilEd, we address the problem of v...
We outline meta-encoding schemas for compiling nonmonotonic logic theories into Verilog HDL (Hardware Description Language) descriptions. These descriptions can be synthesized int...
We describe a method for cascading Description Logic (DL) representation and reasoning on the one hand, and HTN action planning on the other. The planning domain description as wel...
Abstract. By introducing a parallel extension rule that is aware of independence of the introduced extension variables, a calculus for quantified propositional logic is obtained w...
We show how extensible records with structural subtyping can be represented directly in Higher-Order Logic (HOL). Exploiting some specific properties of HOL, this encoding turns o...