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JUCS
2000
120views more  JUCS 2000»
15 years 6 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
ICSM
1999
IEEE
15 years 11 months ago
A Two-Phase Process for Software Architecture Improvement
Software architecture is important for large systems in which it is the main means for, among other things, controlling complexity. Current ideas on software architectures were no...
René L. Krikhaar, André Postma, M. P...
COMPSAC
1997
IEEE
15 years 11 months ago
Classifying Architectural Elements as a Foundation for Mechanism Matching
Building a system at the architectural level can be thought of as decomposition into components followed by a series of exercises in matching. Components must be composed with eac...
Rick Kazman, Paul C. Clements, Leonard J. Bass, Gr...
CASES
2005
ACM
15 years 8 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...