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ISQED
2007
IEEE
124views Hardware» more  ISQED 2007»
16 years 29 days ago
Multi-Dimensional Circuit and Micro-Architecture Level Optimization
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonock...
IEEEARES
2010
IEEE
15 years 12 months ago
Architecture-Aware Adaptive Deployment of Contextual Security Policies
—Deploying a security policy may prove difficult whenever the system does not embed all necessary security functionalities. Some specific functionalities are required to accura...
Stere Preda, Nora Cuppens-Boulahia, Fréd&ea...
RTSS
2003
IEEE
15 years 12 months ago
Impact of PCI-Bus Load on Applications in a PC Architecture
Any data exchanged between the processor and main memory uses the memory bus, sharing it with data exchanged between I/O devices and main memory. If the processor and a device try...
Sebastian Schönberg
168
Voted
ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
15 years 11 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
ETRICS
2006
15 years 10 months ago
Optimized Workflow Authorization in Service Oriented Architectures
Abstract. Complex business processes are usually realized by specifying the integration and interaction of smaller modular software components. For example, hitherto monolithic ent...
Martin Wimmer, Martina-Cezara Albutiu, Alfons Kemp...