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DAC
2008
ACM
16 years 7 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 10 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ASPDAC
2007
ACM
106views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Bisection Based Placement for the X Architecture
Rising interconnect delay and power consumption have motivated the investigation of alternative integrated circuit routing architectures. In particular, the X Architecture, which ...
Satoshi Ono, Sameer Tilak, Patrick H. Madden
PUK
2003
15 years 8 months ago
Modeling in an Architectural Variability Description Language
In order to handle the large amount of variability in product families, automated product derivation support is desirable. To make automated product derivation possible one importa...
Theo Dirk Meijler, Silvie Schoenmaker, Egbert de R...
ICCAD
2007
IEEE
116views Hardware» more  ICCAD 2007»
16 years 3 months ago
Device and architecture concurrent optimization for FPGA transient soft error rate
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
Yan Lin, Lei He