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FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
16 years 1 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
CASES
2006
ACM
15 years 10 months ago
State space reconfigurability: an implementation architecture for self modifying finite automata
Many embedded systems exhibit temporally and behaviorally disjoint behavior slices. When such behaviors are captured by state machines, the current design flow will capture it as ...
Ka-Ming Keung, Akhilesh Tyagi
ENGL
2008
100views more  ENGL 2008»
15 years 7 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid
CGO
2008
IEEE
16 years 1 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic
VLSI
2007
Springer
16 years 29 days ago
A low-power deblocking filter architecture for H.264 advanced video coding
Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking ...
Jaemoon Kim, Sangkwon Na, Chong-Min Kyung