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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
16 years 1 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
CODES
2007
IEEE
16 years 1 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
16 years 1 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
186
Voted
IWSOC
2005
IEEE
131views Hardware» more  IWSOC 2005»
16 years 12 days ago
Very High Radix Scalable Montgomery Multipliers
This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Koç scalable architecture using w × v – bit integer multipliers in place of...
Kyle Kelley, David Harris
EDM
2009
147views Data Mining» more  EDM 2009»
15 years 4 months ago
an Argument Learning Environment Using Agent-Based ITS (ALES)
This paper presents an agent-based educational environment to teach argument analysis (ALES). The idea is based on the Argumentation Interchange Format Ontology (AIF) using "W...
Safia Abbas, Hajime Sawamura