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ASPLOS
2004
ACM
16 years 4 days ago
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign
Tracing garbage collectors traverse references from live program variables, transitively tracing out the closure of live objects. Memory accesses incurred during tracing are essen...
Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykuma...
CODES
2004
IEEE
15 years 10 months ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
AUIC
2006
IEEE
16 years 23 days ago
Virtual planning rooms (ViPR): a 3D visualisation environment for hierarchical information
The Future Operations Centre Analysis Laboratory (FOCAL) at Australia’s Defence Science and Technology Organisation (DSTO) is aimed at exploring new paradigms for situation awar...
Michael Broughton
CASES
2001
ACM
15 years 10 months ago
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, ...
CBSE
2009
Springer
16 years 1 months ago
Integrating Functional and Architectural Views of Reactive Systems
An integrated model-based development approach has to capture the relationship between requirements, design, and implementation models. In the requirements engineering phase, the m...
Jewgenij Botaschanjan, Alexander Harhurin