Flexible and efficient runtime design requires an understanding of the dependencies among the components internal to the runtime and those between the application and the runtime...
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
This paper addresses battery-aware static scheduling in batterypowered distributed real-time embedded systems. As suggested by previous work, reducing the discharge current level ...
We present a methodology for microarchitectural customization of embedded processors by exploiting application information, thus attaining the twin benefits of processor standardi...