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ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
15 years 11 months ago
On optimal physical synthesis of sleep transistors
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
Changbo Long, Jinjun Xiong, Lei He
ISMVL
2003
IEEE
80views Hardware» more  ISMVL 2003»
15 years 11 months ago
Augmented Sifting of Multiple-Valued Decision Diagrams
Discrete functions are now commonly represented by binary (BDD) and multiple-valued (MDD) decision diagrams. Sifting is an effective heuristic technique which applies adjacent var...
D. Michael Miller, Rolf Drechsler
ITC
2003
IEEE
124views Hardware» more  ITC 2003»
15 years 11 months ago
Power-aware NoC Reuse on the Testing of Core-based Systems
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
Érika F. Cota, Luigi Carro, Flávio R...
SBCCI
2003
ACM
94views VLSI» more  SBCCI 2003»
15 years 11 months ago
A New Pipelined Array Architecture for Signed Multiplication
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
Eduardo A. C. da Costa, Sergio Bampi, José ...
CONCUR
2003
Springer
15 years 11 months ago
Multi-Valued Model Checking via Classical Model Checking
Multi-valued model-checking is an extension of classical model-checking to reasoning about systems with uncertain information, which are common during early design stages. The addi...
Arie Gurfinkel, Marsha Chechik