Sciweavers

2719 search results - page 369 / 544
» Exposing Application Alternatives
Sort
View
IPPS
2007
IEEE
16 years 24 days ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
IPPS
2007
IEEE
16 years 24 days ago
The Design and Implementation of Checkpoint/Restart Process Fault Tolerance for Open MPI
To be able to fully exploit ever larger computing platforms, modern HPC applications and system software must be able to tolerate inevitable faults. Historically, MPI implementati...
Joshua Hursey, Jeffrey M. Squyres, Timothy Mattox,...
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
16 years 23 days ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...
MICRO
2007
IEEE
103views Hardware» more  MICRO 2007»
16 years 23 days ago
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Parameter variation is detrimental to a processor’s frequency and leakage power. One proposed technique to mitigate it is Fine-Grain Body Biasing (FGBB), where different parts o...
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Jose...
NCA
2007
IEEE
16 years 23 days ago
Exploiting Host Name Locality for Reduced Stretch P2P Routing
Structured P2P networks are a promising alternative for engineering new distributed services and for replacing existing distributed services like DNS. Providing competitive perfor...
Gert Pfeifer, Christof Fetzer, Thomas Hohnstein