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CODES
2008
IEEE
16 years 1 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
TRIDENTCOM
2008
IEEE
16 years 1 months ago
Virtual integrated TCP testbed (VITT)
Research on TCP performance relies either on simulation programs, which run on a single machine, or on the use of real testbeds, where different machines represent different netwo...
Carlo Caini, Rosario Firrincieli, Renzo Davoli, Da...
AINA
2007
IEEE
16 years 1 months ago
How to Study Wireless Mesh Networks: A hybrid Testbed Approach
— Simulation is the most famous way to study wireless an mobile networks since they offer a convenient combination of flexibility and controllability. However, their largest dis...
Alexander Zimmermann, Mesut Günes, Martin Wen...
CODES
2007
IEEE
16 years 1 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
181
Voted
CODES
2007
IEEE
16 years 1 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Chong Sun, Li Shang, Robert P. Dick
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