Sciweavers

2774 search results - page 193 / 555
» Exploiting Deep Structure
Sort
View
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
16 years 17 days ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
MICRO
2006
IEEE
98views Hardware» more  MICRO 2006»
16 years 17 days ago
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...
SASN
2004
ACM
15 years 12 months ago
Location-aware key management scheme for wireless sensor networks
Sensor networks are composed of a large number of low power sensor devices. For secure communication among sensors, secret keys must be established between them. Recently, several...
Dijiang Huang, Manish Mehta 0003, Deep Medhi, Lein...
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 11 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
MICCAI
1998
Springer
15 years 10 months ago
Segmentation and Measurement of the Cortex from 3D MR Images
The cortex is the outermost thin layer of gray matter in the brain; geometric measurement of the cortex helps in understanding brain anatomy and function. In the quantitative analy...
Xiaolan Zeng, Lawrence H. Staib, Robert T. Schultz...