1256 search results - page 98 / 252 » Experiences with the DEVStone benchmark |
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
177
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ISPAN
1999
IEEE
15 years 10 months ago
1999
IEEE
For an effective Internet-based distributed parallel computing platform, Java-Internet Computing Environment (JICE) is designed and implemented with multithreading and remote meth...
144
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ISSS
1999
IEEE
15 years 10 months ago
1999
IEEE
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is...
128
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ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
173
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ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...