1256 search results - page 73 / 252 » Experiences with the DEVStone benchmark |
133
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
152
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CISIS
2010
IEEE
16 years 1 months ago
2010
IEEE
—Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported threads grows in these processors, it may ...
142
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DATE
2008
IEEE
16 years 18 days ago
2008
IEEE
We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We...
144
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ACMMSP
2004
ACM
15 years 11 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
167
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SIGUCCS
2004
ACM
15 years 11 months ago
2004
ACM
Designing computing equipment for a computer laboratory is not easy. In a class in a computer laboratory, it is not unusual that all students do the same thing simultaneously. Tre...