1256 search results - page 137 / 252 » Experiences with the DEVStone benchmark |
139
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
153
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions...
174
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
159
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
180
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...