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» Experiences with the DEVStone benchmark
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ICCAD
2003
IEEE
117views Hardware» more  ICCAD 2003»
16 years 3 months ago
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
PLDI
2009
ACM
16 years 1 months ago
Stretching transactional memory
Transactional memory (TM) is an appealing abstraction for programming multi-core systems. Potential target applications for TM, such as business software and video games, are like...
Aleksandar Dragojevic, Rachid Guerraoui, Michal Ka...
CGO
2008
IEEE
16 years 24 days ago
Cole: compiler optimization level exploration
Modern compilers implement a large number of optimizations which all interact in complex ways, and which all have a different impact on code quality, compilation time, code size,...
Kenneth Hoste, Lieven Eeckhout
MICRO
2007
IEEE
133views Hardware» more  MICRO 2007»
16 years 18 days ago
Revisiting the Sequential Programming Model for Multi-Core
Single-threaded programming is already considered a complicated task. The move to multi-threaded programming only increases the complexity and cost involved in software developmen...
Matthew J. Bridges, Neil Vachharajani, Yun Zhang, ...
ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
16 years 10 days ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren