774 search results - page 53 / 155 » Experiences of low power design implementation and verificat... |
175
click to vote
NOCS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
168
click to vote
GLVLSI
2009
IEEE
16 years 26 days ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
150
click to vote
SPIN
2000
Springer
15 years 9 months ago
2000
Springer
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
140
click to vote
SLIP
2009
ACM
16 years 19 days ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
185
click to vote
SIPS
2006
IEEE
16 years 4 days ago
2006
IEEE
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of the...