774 search results - page 50 / 155 » Experiences of low power design implementation and verificat... |
144
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
171
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DAC
2011
ACM
14 years 6 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
164
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GLOBECOM
2006
IEEE
16 years 5 days ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
156
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IPSN
2004
Springer
15 years 11 months ago
2004
Springer
The performance of a sensor network may be best judged by the quality of application specific information return. The actual sensing performance of a deployed sensor network depe...
130
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...