Static Single Assignment form is an intermediate representation that uses instructions to merge values at each confluent point of the control flow graph. instructions are not ma...
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...