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CF
2009
ACM
16 years 1 months ago
Core monitors: monitoring performance in multicore processors
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A...
SIGCOMM
2009
ACM
16 years 1 months ago
VL2: a scalable and flexible data center network
To be agile and cost effective, data centers should allow dynamic resource allocation across large server pools. In particular, the data center network should enable any server to...
Albert G. Greenberg, James R. Hamilton, Navendu Ja...
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
16 years 1 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
CODES
2007
IEEE
16 years 1 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
16 years 1 months ago
The ARTEMIS cross-domain architecture for embedded systems
platform and a suite of abstract components with which new developments in different application domains can be engineered with minimal effort [1]p.16. Generic platforms, or refere...
Hermann Kopetz
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