453 search results - page 76 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
176
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ANCS
2007
ACM
15 years 10 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
174
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CODES
2006
IEEE
16 years 2 days ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
147
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MICRO
1995
IEEE
15 years 9 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
157
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MICRO
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
144
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IEEEPACT
1998
IEEE
15 years 10 months ago
1998
IEEE
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...