453 search results - page 44 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
144
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DATE
2006
IEEE
16 years 7 days ago
2006
IEEE
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0...
165
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ICPPW
2005
IEEE
15 years 11 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
154
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TCSV
2002
15 years 5 months ago
2002
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
172
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PDP
2008
IEEE
16 years 17 days ago
2008
IEEE
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
190
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ICDM
2007
IEEE
16 years 15 days ago
2007
IEEE
Inspired by emerging multi-core computer architectures, in this paper we present MT CLOSED, a multi-threaded algorithm for frequent closed itemset mining (FCIM). To the best of ou...