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ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
16 years 27 days ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
GECCO
2007
Springer
159views Optimization» more  GECCO 2007»
16 years 23 days ago
A systemic computation platform for the modelling and analysis of processes with natural characteristics
Computation in biology and in conventional computer architectures seem to share some features, yet many of their important characteristics are very different. To address this, [1]...
Erwan Le Martelot, Peter J. Bentley, R. Beau Lotto
AICCSA
2006
IEEE
101views Hardware» more  AICCSA 2006»
16 years 21 days ago
Refactoring Tools and Complementary Techniques
Poorly designed software systems are difficult to understand and maintain. Modifying code in one place could lead to unwanted repercussions elsewhere due to high coupling. Adding ...
Martin Drozdz, Derrick G. Kourie, Bruce W. Watson,...
APCSAC
2005
IEEE
16 years 7 days ago
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkum...
LCTRTS
2005
Springer
16 years 3 days ago
Probabilistic source-level optimisation of embedded programs
Efficient implementation of DSP applications is critical for many embedded systems. Optimising C compilers for embedded processors largely focus on code generation and instructio...
Björn Franke, Michael F. P. O'Boyle, John Tho...