3893 search results - page 496 / 779 » Execution Architectures and Compilation |
138
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ASPDAC
2006
ACM
16 years 19 days ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
195
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PPOPP
2006
ACM
16 years 18 days ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
172
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CODES
2005
IEEE
16 years 8 days ago
2005
IEEE
With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary....
169
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IPPS
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
164
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EUROPAR
2003
Springer
15 years 12 months ago
2003
Springer
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...