3893 search results - page 460 / 779 » Execution Architectures and Compilation |
144
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MICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
212
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MICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
204
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ICS
1997
Tsinghua U.
15 years 11 months ago
1997
Tsinghua U.
Program slicing is an analysis that answers questions such as \Which statements might a ect the computation of variable v at statement s?" or \Which statements depend on the ...
243
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CONCUR
1993
Springer
15 years 10 months ago
1993
Springer
During the course of the last decade, a mathematical model for the parallelization of FOR-loops has become increasingly popular. In this model, a (perfect) nest of r FOR-loops is r...
214
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ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...