Sciweavers

3893 search results - page 433 / 779
» Execution Architectures and Compilation
Sort
View
IEEEPACT
2005
IEEE
16 years 10 days ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
SBACPAD
2003
IEEE
106views Hardware» more  SBACPAD 2003»
16 years 20 hour ago
A Parallel Implementation of the LTSn Method for a Radiative Transfer Problem
— A radiative transfer solver that implements the LTSn method was optimized and parallelized using the MPI message passing communication library. Timing and profiling informatio...
Roberto P. Souto, Haroldo F. de Campos Velho, Step...
ICCS
2003
Springer
15 years 12 months ago
Application Controlled IPC Synchrony - An Event Driven Multithreaded Approach
Interprocess communication (IPC) is an important phenomenon in distributed computing and operating systems. Microkernels of modern operating systems use synchronous IPC semantics f...
Susmit Bagchi, Mads Nygaard
ASPLOS
1998
ACM
15 years 11 months ago
Active Disks: Programming Model, Algorithms and Evaluation
Several application and technology trends indicate that it might be both pro table and feasible to move computation closer to the data that it processes. In this paper, we evaluat...
Anurag Acharya, Mustafa Uysal, Joel H. Saltz
182
Voted
RTAS
1997
IEEE
15 years 11 months ago
OS-Controlled Cache Predictability for Real-Time Systems
3rd IEEE Real-time Technology and Applications Symposium (RTAS), June 1997 in Montreal, Canada Cache-partitioning techniques have been invented to make modern processors with an e...
Jochen Liedtke, Hermann Härtig, Michael Hohmu...