3893 search results - page 326 / 779 » Execution Architectures and Compilation |
211
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ISVLSI
2006
IEEE
16 years 20 days ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
162
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IPPS
1998
IEEE
15 years 11 months ago
1998
IEEE
In distributed-memory message-passing architectures reducing communication cost is extremely important. In this paper, we present a technique to optimize communication globally. O...
172
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DAC
1994
ACM
15 years 10 months ago
1994
ACM
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
159
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DAC
1992
ACM
15 years 10 months ago
1992
ACM
This paper describes a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant ...
179
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...