3893 search results - page 320 / 779 » Execution Architectures and Compilation |
182
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IEEEPACT
1999
IEEE
15 years 11 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
140
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IWPC
1999
IEEE
15 years 11 months ago
1999
IEEE
One of the fundamental problems with the static analysis of binary (executable) code is that7 of recognizing, in a machine-independent way, the target addresses of n-conditional b...
172
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HICSS
1997
IEEE
15 years 11 months ago
1997
IEEE
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
159
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IFL
1997
Springer
15 years 10 months ago
1997
Springer
This paper introduces a new compiler optimization called with-loop-folding. It is based on a special loop construct, the withloop, which in the functional language Sac (for Single ...
148
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CEC
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...