3893 search results - page 304 / 779 » Execution Architectures and Compilation |
184
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ICS
1999
Tsinghua U.
15 years 11 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
161
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MICRO
1998
IEEE
15 years 11 months ago
1998
IEEE
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
136
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ISSS
1995
IEEE
15 years 10 months ago
1995
IEEE
The increasing usage of Application Specific Instruction Set Processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicat...
176
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CORR
2010
Springer
15 years 6 months ago
2010
Springer
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
175
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VLSISP
2008
15 years 6 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...