3893 search results - page 294 / 779 » Execution Architectures and Compilation |
170
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ISCAS
2006
IEEE
16 years 19 days ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
179
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IEAAIE
2004
Springer
2004
Springer
The Cognitive Controller: A Hybrid, Deliberative/Reactive Control Architecture for Autonomous Robots
15 years 12 months ago
Abstract. The Cognitive Controller (CoCo) is a new, three-tiered control architecture for autonomous agents that combines reactive and deliberative components. A behaviour-based re...
176
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IPPS
2003
IEEE
15 years 12 months ago
2003
IEEE
Aim of the paper is to develop a concise but comprehensive analytical model for the well-known Grace Hash Join algorithm on cost effective cluster architectures. This approach is ...
188
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RIDE
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper addresses the issue of developing agents capable of participating in several potentially simultaneous auctions of different kinds (English, First-Price, Vickrey), with ...
196
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DEXAW
2000
IEEE
15 years 11 months ago
2000
IEEE
Holonic Manufacturing Systems have emerged over the last seven years as strategy for manufacturing control system design. A new approach called Holonic ComponentBased Architecture...