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TSMC
1998
62views more  TSMC 1998»
15 years 6 months ago
Performance based design of high-level language-directed computer architectures
— This paper is concerned with the analytical modeling of computer architectures to aid in the design of high-level language-directed computer architectures. High-level language-...
Rajendra S. Katti, Mark L. Manwaring
HPCA
2001
IEEE
16 years 7 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
16 years 20 days ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
WAC
2004
Springer
150views Communications» more  WAC 2004»
15 years 12 months ago
A Systems Architecture for Sensor Networks Based On Hardware/Software Co-design
We describe the motivation and design of a novel embedded systems architecture for large networks of small devices, tha canonical example being wireless sensor networks. The archit...
Andy Nisbet, Simon Dobson
DATE
2002
IEEE
118views Hardware» more  DATE 2002»
15 years 11 months ago
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
Marcos Sanchez-Elez, Milagros Fernández, Ra...