3893 search results - page 286 / 779 » Execution Architectures and Compilation |
161
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CSEE
2007
Springer
16 years 24 days ago
2007
Springer
This paper reports experiences from an experiment in a software architecture course where the focus was both on giving students valuable education as well as getting important emp...
187
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EUROPAR
2007
Springer
16 years 23 days ago
2007
Springer
We show empirically that some of the issues that affected the design of linear algebra libraries for distributed memory architectures will also likely affect such libraries for s...
186
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ISCAS
2003
IEEE
15 years 12 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
129
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
176
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ETS
2010
IEEE
15 years 7 months ago
2010
IEEE
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...