502 search results - page 75 / 101 » Evolving Hardware on a Large Scale |
152
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
169
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MICRO
2009
IEEE
16 years 21 days ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
165
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ISCA
2010
IEEE
15 years 11 months ago
2010
IEEE
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
196
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BMCBI
2011
14 years 9 months ago
2011
Background: High-throughput mass spectrometry (MS) proteomics data is increasingly being used to complement traditional structural genome annotation methods. To keep pace with the...
175
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IEEEPACT
1998
IEEE
15 years 10 months ago
1998
IEEE
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...