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» Evolving Hardware on a Large Scale
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DATE
2010
IEEE
109views Hardware» more  DATE 2010»
15 years 11 months ago
TIMBER: Time borrowing and error relaying for online timing error resilience
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
15 years 11 months ago
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong,...
ISQED
2002
IEEE
111views Hardware» more  ISQED 2002»
15 years 11 months ago
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm
This paper presents a fast algorithm to optimize both the widths and lengths of power/ground networks under reliability and power dip/ground bounce constraints. The spacesizing wh...
Ting-Yuan Wang, Charlie Chung-Ping Chen
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
15 years 10 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
ICCAD
1998
IEEE
93views Hardware» more  ICCAD 1998»
15 years 10 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong