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» Evolving Hardware on a Large Scale
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ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
15 years 11 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
WMPI
2004
ACM
15 years 11 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
SIGCOMM
2000
ACM
15 years 10 months ago
SmartBridge: A scalable bridge architecture
As the number of hosts attached to a network increases beyond what can be connected by a single local area network (LAN), forwarding packets between hosts on different LANs become...
Thomas L. Rodeheffer, Chandramohan A. Thekkath, Da...
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
16 years 22 days ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 9 months ago
Power management of online data-intensive services
Much of the success of the Internet services model can be attributed to the popularity of a class of workloads that we call Online Data-Intensive (OLDI) services. These workloads ...
David Meisner, Christopher M. Sadler, Luiz Andr&ea...