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ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
15 years 6 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
SIGMETRICS
2008
ACM
111views Hardware» more  SIGMETRICS 2008»
15 years 6 months ago
Predicting the resource consumption of network intrusion detection systems
Abstract. When installing network intrusion detection systems (NIDSs), operators are faced with a large number of parameters and analysis options for tuning trade-offs between dete...
Holger Dreger, Anja Feldmann, Vern Paxson, Robin S...
CLUSTER
2002
IEEE
15 years 11 months ago
Leveraging Standard Core Technologies to Programmatically Build Linux Cluster Appliances
Clusters have made the jump from lab prototypes to fullfledged production computing platforms. The number, variety, and specialized configurations of these machines are increasi...
Mason J. Katz, Philip M. Papadopoulos, Greg Bruno
IEEEPACT
2007
IEEE
16 years 12 days ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
13 years 8 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...